XJTAG lauched the XJTAG DFT Assistant for Altium Designer at Embedded World 2016, Nuremberg, Germany. Developed by XJTAG, the free software extension for Altium Designer significantly increases the Design for Test capabilities of the unified schematic capture and PCB design system

Modern printed circuit boards (PCBs) are increasingly densely populated and access to pins under many packages, such as Ball Grid Array (BGA) or Land Grid Array (LGA), is virtually impossible.

This is a major challenge for any test equipment that relies on physical contact to a node or pin. As boundary scan was designed to be the practical solution to this challenge, it has become vitally important to get the boundary scan chain right at the design stage. XJTAG DFT Assistant for Altium Designer helps validate correct boundary scan chain connectivity, through full integration with Altium Designer.

“The XJTAG DFT Assistant for Altium Designer provides engineers with a free, easy to use extension to check if boundary scan chains are correctly connected and terminated at the schematic capture stage, long before the PCB is produced. By detecting and correcting these faults earlier, companies do save both time and money.” commented Simon Payne, CEO, XJTAG. “While the first prototype is being manufactured, XJTAG DFT Assistant allows you to export a preliminary XJTAG project from Altium Designer to the XJTAG development software, where additional tests can be developed. These can then be used to test real hardware as soon as it’s available. This provides a vital new capability to electronic engineers everywhere.”

The XJTAG DFT Assistant for Altium Designer comprises two key elements; the XJTAG Chain Checker, and the XJTAG Access Viewer. XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected Test Access Ports (TAPs). A single connection error would inhibit an entire scan chain from working, XJTAG Chain Checker identifies connection errors and reports them to the developer during the design process. Incorrectly terminated TAPs are also identified.

XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage could be further extended.

Boundary scan, as defined by the IEEE 1149.x family of standards and adopted by all leading semiconductor manufacturers, provides electrical access to compliant integrated components on a PCB using a boundary scan chain; a simple 4- or 5-signal bus that sequentially connects JTAG-enabled devices. Through boundary scan, access can be further extended to include non JTAG-enabled devices for connectivity and functional testing, as well as non-volatile memory and FPGA/CPLD programming.

Useful from prototype bring-up to production test, boundary scan allows a wide range of faults to be detected, such as short circuits, open circuits, stuck-at high/low faults and missing pull-up/down resistors. XJTAG’s products also allow faults to be located to specific nets, without the need for physical access to pins or expensive In-Circuit Testers, Flying Probe or Bed-of-Nail test fixtures.

XJTAG DFT Assistant for Altium Designer is a free extension downloadable from the Extensions panel.

To find out more, visit www.xjtag.com or contact us at enquiries@xjtag.com.