Teledyne e2v, specialist in semiconductor, quantum tech and RF applications, have revealed their latest IP: ESIstream, an open source, serial data interface protocol designed with minimal overhead, lower complexity, a reduction in link latency/ease of attaining deterministic latency, all of which can be integrated into a range of targeted FPGA architectures.
Around the turn of the millennia, advances in data convertor technology, as well as CMOS processes, were starting to hit functional limits. Originally high-speed ADCs and DACs (fs > 10 MHz) featured parallel data interfaces, meaning that a significant number of printed circuit board (PCB) traces had to be run to/from each convertor. ESIstream intends to simplify this through its singular protocol, with ease of implementation. For specifications, ESIstream uses a 14b/16b data encoding algorithm, least significant bit first and supports lane rates in excess of 13 Gbps. It suits 12- and 14-bit resolution converters. The protocol uses a linear feedback shift register scrambling process and adds both a disparity and clock synchronisation bits (2 bit overhead) to each data word.
This is a stripped down definition of what ESIstream has to offer, but Teledyne affirms that it matches the performance levels provided by JESD204B, offering a valuable user experience. Now, with the introduction and availability of trusted IP blocks and VHDL code modules for both Rx and Tx blocks compatible with industry standard FPGAs, ESIstream hopes to cross the last hurdle.
If you wish to read more on what ESIstream has to offer the industry, Teledyne has released a white paper covering its specifications, the possibility of attaining deterministic latency, among other key points hinted at in this summary: relevant articles and specs can be found if you click here.
Otherwise, visit Teledyne e2v’s website for a direct overview through here.
