SureCore is opening its low power memory compiler to qualifying companies for 30 days, so as to evaluate the capabilities of its PowerMiser and EverOn standard SRAM IP products on low power metrics. The new service will prove particularly useful for constraint and compute intensive SoC designs.
This Compiler Access Program (CAP) is the newest service for the company’s low-power SRAM IPs, of which many are implemented in CMOS and SOI processes. CAP is available to SoC designers to evaluate the performance and low power capabilities of SureCore’s low power SRAM on these CMOS and SOI process technologies, suitable for the following dimensions: 22nm, 28nm or 40nm.
“AI, imaging, IoT, medical & wearable devices all require enhanced power profiles. With SRAM integration levels continuing to rise, our standard products help deliver the power savings needed in these competitive market spaces,” explains Paul Wells, SureCore’s CEO: “Through CAP, we’re opening a low power memory test drive to optimise power budgets and manufacturability.”
Companies qualifying for CAP receive a link and password, plus the Compiler User Guide. Designers can then explore optimal performance/lowest power SRAM that meets project requirements. The programme will subsequently generate datasheets that cover detailed PPA information, including access times, dynamic power, and sleep/deep sleep/standby leakage power, based on the requested instances and operating environment.