The concept behind advanced 3D packaging is to stack multiple dies or wafers in a vertical direction – or Z-dimension – to achieve better performance, with lower power requirements, smaller size and lower cost.

However, as 3D packages become increasingly complex, so do the challenges in identifying defects in multiple layers of stacked dies, silicon interposers and interconnections, such as through-silicon vias (TSVs) and fine-pitch micro-bumps.  

With less accessibility to internal components, and a need to scan multiple, stacked layers, the focus is now shifting to methods of non-destructive testing, both in manufacturing and for failure analysis.

3D Advanced Packaging

In general, the term 3D packaging applies to products manufactured by stacking silicon wafers or dies and interconnecting them vertically.  This covers many integration schemes, including 3D wafer-level packaging, system in package (SiP), package on package (PoP), 2.5D and 3D, stacked ICs and other forms of heterogeneous integration. 

To achieve vertical stacking, early 3D packages relied on interconnects such as wire bonding and flip chips.  Today, communication between chips often involves a silicon or organic interposer or bridge, with TSVs. The interposer acts as the bridge between the chips and the board, while increasing the I/Os and bandwidth.

This approach has been embraced by Intel, which recently announced its new Foveros 3D packaging technology that allows complex, heterogenous logic chips to be stacked directly on top of each other.

The Defense Advanced Research Projects Agency (DARPA), an agency of the U.S. Department of Defense, already plans to develop a large catalogue of third-party chiplets for commercial, military and aerospace applications.  

Non-Destructive Testing of 3D Packages

The challenge today is to perform 100 per cent inspection with relatively high throughput to identify and remove 3D packages or components that do not meet quality requirements.  

Among the available non-destructive methods, Scanning Acoustic Microscopy (SAM) is the most widely used technique for testing and failure analysis involving stacked dies or wafers.

SAM utilises ultrasound waves to non-destructively examine internal structures, interfaces and surfaces of opaque substrates. The resulting acoustic signatures can be constructed into 3-dimensional images that are analysed to detect and characterise device flaws such as cracks, delamination, inclusions and voids in bonding interfaces, as well as to evaluate soldering and other interface connections.

The unique characteristic of acoustic microscopy is its ability to image the interaction of acoustic waves with the elastic properties of a specimen. In this way, the microscope is used to image the interior of an opaque material. 

To produce an image, samples are scanned point by point and line by line. Scanning modes range from single layer views to tray scans and cross-sections. Multi-layer scans can include up to 50 independent layers. Images from different depths can be combined into a single scan as well, called Tomographic Acoustic Micro Imaging (TAMI).    

“Scanning Acoustic Microscopy provides non-destructive imaging of defects and delaminations in die and package materials,” says Lisa Logan, applications manager  of Scanning Acoustic Microscopes for PVA TePla Analytical Systems, a company that designs and manufactures advanced Scanning Acoustic Microscopes for both laboratory and production environments.

“SAM is particularly useful for inspection of small, complex three-dimensional devices,” adds Logan: “The equipment is highly sensitive to the presence of delaminations and air-gaps at sub-micron thicknesses.”

According to Logan, several leading suppliers of programmable logic devices have already evaluated and purchased high resolution SAM equipment for non-destructive analysis of next generation 3D products to scan for packaging anomalies.