Noise reduction technology has been developed by Toshiba Corporation that reduces jitter in radio-frequency signals, cutting phase noise by up to 90 percent. This enables a further migration to high-speed wireless communication chips for wireless LAN and WiMAX.

Radio frequency phased locked loops (PLL) in mobile communication LSI chips were typically structured with analogue and digital circuits.

As achieving ultra-fine analogue circuits is highly challenging, there is now a shift to all digital PLL using time-to-digital converters (TDC).

While digitisation reduces circuit size it also increases phase noise-a degrading displacement in the pulse of a radio frequency signal-due to larger delay in the TDC’s inverter circuits.

Cutting phase noise is essential for high-speed communication standards, like WiMAX, which require highly accurate signals.

There is the concern that current TDC is sensitive to variations in manufacturing processes that impact on their performance.

This raises a need for more robust manufacturability.

To reduce susceptibility variations in mass production and suppress phase noise, the company developed a new TDC integrating an interpolation circuit that uses a low resistance conductor to connect the output of two inverters.

A triple interpolation splits the cycle of output signal of frequency synthesisers, and reduces phase noise by 90 percent.

The solution achieves a PLL with stable performance, as it utilises a stable waveform.