The next generation Xilinx ISE Design Suite 13.3 has been released. The tool has been enhanced with new features and capabilities so DSP designers can more easily implement bit-accurate single, double and full custom precision floating-point math operations in their designs.

The tool targets wireless, medical, aerospace and defence, high performance computing and video applications.

The flow is available through the System Generator for DSP and utilises the company’s Floating-Point Operator IP.

The combination of single, double and full custom precision floating-point with the System Generator provides DSP designers an environment to easily create, simulate and implement floating-point designs, as well as have more control over the silicon area and to attain the required power.

The Floating-Point Operator core allows a range of floating-point arithmetic operations that can be performed in an FPGA.

The operation is specified when the core is generated and now the System Generator, and each operation variant has a AXI-4 streaming interface.

Previously, it was possible to implement a floating-point design in an FPGA leveraging the full custom precision floating-point IP available.

However, the design flow required an understanding of VHDL or Verilog and simulation could be challenging for DSP developers.

With the availability of the new design suite, designers can now enhance their systems from a higher level of abstraction.