James Stanbridge of JTAG Technologies discusses how delivering value-added functionality is the driving force behind boundary-scan tool development
As many engineers involved with manufacturing and test will know, boundary-scan (a.k.a. JTAG) is a technology that has been around for more than 20 years. However, for many, it has also been a nebulous technology, one perceived as: difficult (to understand and implement); expensive (to buy-in either as a service or as a software package); and incomplete (with respect to fault coverage, for example).
Many of these preconceptions might once have been justified. Now, circa 22 years after the initial JTAG committee had their work ratified by the IEEE standards committee as IEEE Std. 1149.1, nothing could be further from the truth. As in any mature marketplace where technology advances, software becomes more sophisticated and faster, levels of automation are improved, hardware becomes more proficient and best of all for prospective users, prices come down.
Boundary-scan technology is simple enough to understand and to implement. In essence, any chip that is compliant with IEEE Std. 1149.1 has an additional set of pins comprising test data input (TDI), test data output (TDO), test clock, test mode and optionally test reset. These make up the JTAG Test Access Port (TAP).
By connecting an electrical interface to the TAP an engineer can access a built-in test feature of these chips known as the boundary-scan register (BSR). In turn the BSR cells connect to the input and output pins of the device.
Using the test clock to load data serially through TDI into the BSR the test engineer can control (digital) output pins or sense (logic) values at input pins. The TDO line can then connect back to the controller interface or link to another device’s TDI to form a scan chain (see figure 1). Thus, the minimum design input that is needed to use JTAG/boundary-scan is the layout of the JTAG TAP signals.
Of course it’s not always quite that simple, as some devices might not comply fully with the standard. Furthermore, when attempting to use a fast clock, signal terminations come into play and for this reason most JTAG vendors offer design-for-test guidelines (see figure 2).
Latest tools and features
JTAG Technologies is typical of a boundary-scan company now offering ‘more for less’. For example, its ProVision application generation software includes a host of features that help improve fault coverage. Users will start by importing netlist information from an EDA tool from the likes of Altium, Cadence, OrCAD or Mentor; in fact over 30 netlist formats are supported.
This data is then processed by the software which adds the pin-to-pin connectivity data to the project database. At the same time a component list is stripped from the EDA input and device models from the software’s database are mapped to each non-JTAG part.
Here, such parts will typically include passives (resistors, resistor packs, connectors etc.), discrete logic devices (7400 series, RX/TX parts, drivers etc.) and memories (including Flash, SPI ROM, DDR RAM) as well as other parts such a ADC, DACs, DC-DC converters and crystals.
JTAG-compliant devices are described by BSDL models; usually available from the manufacturer’s website. These models contain a concise description of the boundary-scan functionality.
Once a project database has been established, through netlist import and model assignments, the application developer can choose from a host of generation options that will allow many test and programming operations to be created automatically. These will include: Scan path infrastructure test; Shorts/open interconnect test on boundary-scan pins/nets; Functional logic ‘cluster’ tests (e.g. on 7400 series parts, I2C parts ADCs etc.); Memory interface cluster tests; Flash memory programmer sets; Serial PROM programmer sets; and CPLD and config PROM programming.
In addition to the automated test feature mentioned above, most systems should incorporate some added value features. Typically these will include a scripting system that uses structured programming language to create more advanced tests for devices that might require loops and conditional branching.
Another feature gaining in popularity is the use of microprocessor and DSP core on-chip debug modes to enable more comprehensive and/or faster testing of the processor peripheral devices. For instance, the company offers a range of core access and control routines, called CoreCommander, that support ARM, Marvel, TI and Freescale processor cores.
With the standard automated tests plus extra features, boundary-scan developers can build-up considerable amounts of fault coverage that would have been unthinkable in the early days of the standard.
In the company’s ProVision software, for example, the fault coverage statistics are tabulated automatically. What’s more, they can be ‘overlaid’ onto a schematic or layout diagram provided by a complementary Visualiser tool.
On a predominantly digital design, fault coverage statistics in excess of 80 percent nets/nodes are not uncommon. Even on mixed signal designs that use a combination of digital and analogue parts, boundary-scan can be used to tackle the hard-to-get-at high pin density parts that are often the most susceptible to faulty assembly during the manufacturing processes.
The cost-effectiveness of these tools is the main factor driving the technology forward. For instance, 20 years ago a set of basic test generators/executors with limited capability would have cost £16K or more (almost £35K in today’s money). Now, a fully automated ‘second generation’ test system can be purchased for less than half that price. Also, more basic systems that rely only on scripting routines that offer logic cluster testing, using an open-source engineering orientated language such as Python, can be purchased for circa £1200.
JTAG Technologies
