Microchip announces four new differential clock buffers that move past jitter standards for next-generation data centre applications.

The ZL40292 and ZL40293 are specifically designed to meet the new DB2000Q specification, while the ZL40294 and ZL40295 are designed to meet the DB2000QL industry standard. These new devices also meet PCIe Gen 1, 2, 3 and 4 specifications. 

Each buffer cushions its respective chipsets, where distributed clocks are required across several peripheral components, such as central processing units (CPUs), field programmable gate arrays (FPGAs) and physical layers (PHYs) in data centre servers and storage devices, along with many other PCIe applications. These devices will minimise jitter when distributing clocks to up to 20 outputs, thereby maintaining the integrity and quality of the clock signal through the buffer. 

The new buffers achieve low power dissipation and contribute significant savings to power budgets by using low-power, high-speed current steering logic (LP-HCSL). Compared to standard HCSL, LP-HCSL consumes one third of the power, resulting in a noteworthy decrease in power consumption. This gives customers the ability to drive longer traces on their board, which benefits signal routing while reducing component and board space.

For more information, click the following links:

ZL40292 and ZL40293 for DB2000Q

ZL40294 and ZL40295 for DB2000QL