James Stanbridge, UK Sales Manager at JTAG Technologies, explores the transition of boundary-scan from high-end test tools to low-cost and in some cases free, aid to hardware design/debug
The JTAG, a.k.a. IEEE Std. 1149.1 boundary-scan test architecture, was first devised more than 20 years ago. With such tools a test engineer could extract basic design information from the design team’s EDA tools and quickly create structural tests for detecting short- and open-circuits and perform simple logic tests. They could also create device programming applications for CPLDs, SPROM, Flash memories and so on.
Over the years tools have improved in many aspects, including overall effectiveness, quality of test generation, ease-of-use and integration with other test methods (such as flying probe, bed-of-nails, functional etc…)
However, in nearly all cases, the improvements and enhancements were aimed at test engineers and the tools themselves attracted a price tag that was considered a ‘reasonable’ expense for optimising the production process and maintaining high-yields.
Accordingly, the tools remained inaccessible to other interested parties, such as the design fraternity.
While JTAG was developing its structural test technique for production purposes the standard (or rather the JTAG test access port [TAP]) was also being utilised by silicon vendors for alternative uses.
Today a growing number of designers are realising the true potential of the ‘hidden’ boundary-scan features; most notably its usefulness as a means of debugging prototype hardware.
There are also the benefits of introducing JTAG/boundary-scan testing into production cycles much earlier. However, designers are not used to paying production tool prices for their development tools.
The past couple of years though have witnessed some interesting developments, starting with the launch in November 2009 of a completely free, albeit basic, boundary-scan debug software tool called: JTAGLive (www.jtaglive.com).
A built-in ‘Buzz’ utility, analogous to a multi-meter, enables users to perform practically instant pin-to-pin continuity tests, exercise multiple (up to 10) nets in the measure mode and also use a boundary-scan SAMPLE instruction to monitor activity on a given pin (a la logic probe). The tool-set even runs on existing design interface hardware such as Altera’s USB Blaster and Xilinx programming ‘cables’.
Free software for engineers
In addition to the arrival of free tools the industry is also experiencing an influx of attractively priced software and hardware ‘bundles’, aimed at the designer-cum-test engineer. One in particular is the ProVision Designer Station (PV_DST). Launched earlier this year, it is pitched as ‘a flexible, low-cost development system for the preparation of all boundary-scan test routines’.
So what functionality has been brought to the design community? This is best answered by considering PV_DST in action. Following start-up a project wizard prompts the user to add netlist information that is usually gathered from the designer’s schematic entry tool.
Multiple netlists can be added to an individual project making it simple to support ‘stacked’ designs comprising main boards and mezzanine cards and/or system cards in a plug-in back-plane.
An interconnect test can often contribute over 80 percent of a digital board’s fault coverage if most of the high pin-count parts are JTAG (IEEE Std.1149.1) compliant. Moreover, using the JFT and/or ActiveTest modules, users can ‘top-up’ the fault coverage to get figures of up to 95 percent of nets and pins tested using boundary-scan by implementing cluster tests (a type of functional test targeted at a specific device or device group).
As more and more designers see the benefits of improved time-to-market due to a less frustrating debug phase, the use of the standard for hardware debug is expected to increase rapidly and the cost of tools will fall even further. It is also feasible to expect that on-chip debug features of chips will provide further opportunities to increase test coverage via the now venerable JTAG port.
JTAG Technologies
