A hierarchical RTL-to-GDSII reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology has been released by Magma Design Automation. The tool utilises the Talus IC implementation system’s power optimisation and management capabilities, ARM Artisan 32/28-nm LP process libraries and the Common Platform alliance’s advanced 32/28-nm process technology to enable designers to reduce power, turnaround time and cost per die.
The hierarchical reference design was developed using the company’s Talus RTL-to-GDSII flow and the latest ARM Artisan 32/28-nm LP libraries, optimised for the Common Platform 32/28LP process libraries; standard cells, memory compilers and general-purpose IOs. The flow provides key low-power design capabilities, including an automated multiple voltage-domain design methodology, validates tool and library interoperability and facilitates rapid user adoption through a sample design which can be accessed from Magma or the Common Platform alliance.
The Reference Flow is an integrated RTL-to-GDSII that is based on Talus Design, Talus Vortex, Hydra and Talus Power Pro. It provides a comprehensive low-power hierarchical solution. Talus Design and Talus Vortex provide an advanced IC implementation solution that performs timing optimisation concurrently during routing – rather than sequentially before and after place and route – providing faster overall design closure with better performance and predictability. Hydra is a hierarchical design planning solution for large systems on a chip (SoCs) and features out-of-the-box reference flows for enhanced ease of use and faster delivery of better floorplans. Talus Power Pro supports power optimisation techniques required in low-power designs.
