Going up to the next physical layer

The Serial RapidIO Gen2 specification includes significant enhancements to the physical, logical and transaction layers. It has doubled the per-lane performance to 6.25 Gbaud, doubled the target transmission distance to 100 cm of FR4 and two connectors, while simultaneously reducing the bit error rate (BER) by three orders of magnitude (to 10-15).

The specification includes new port lane widths of 2x, 8x and 16x to complement the 1x and 4x from the Gen 1 specification. Many endpoint and switch devices that have entered the market support 4x, 2x and 1x ports for up to 20 Gigabits per second of raw throughput, which more than doubles the capacity of 10 Gigabit Ethernet solutions and surpasses PCI Express Gen2 by 25 percent.

The specification covers all the electrical specifications for short-, medium- and long-reach transmitters and receivers, including eye masks where appropriate. Unlike Gen1, the Gen2 specification requires equalisation at 6.25 Gbaud for all reaches. At 5 Gbaud, it will likely be needed for long reach, and is optional for short and medium reach.

One BER characterisation feature that is new in the Serial RapidIO Gen2 is the per-lane 8b/10b decode error counter. This provides a very good indication of the true BER for reasonably healthy lines with a BER of approximately 10-9 or better.

SerDes: Equalisation, on-die scope, BER testing

IDT recently announced the availability of it’s CPS-1848 and CPS-1616 Gen2 switches. To meet the stringent specification characteristics, the company designed a 6.25 Gbaud receiver that employs Continuous Time Equalisation (CTE) and Decision Feedback Equalisation (DFE).

CTE provides a single zero to boost amplification of the frequency of interest. This is an active amplification, but is performed in a passive fashion on all received bits. This improves the gain of the received signal, while minimising noise gain. A five-tap DFE was also employed. DFE provides very selective gain while simultaneously minimising noise when boosting signals.

A variety of features were developed to minimise power. For example, the transmitter provides a great degree of swing control. The user does not have to stick with what’s required in the standard at the expense of BER. At the receiver, a half-rate clock provides significant power savings. This architecture splits the receive data path into even and odd bits, and then leverages a clock running at half the clock speed. Regarding DFE, features that minimise power include, allowing the user to turn off unused taps.

To minimise noise on the SerDes, decoupling capacitors are used to fill in all available silicon space to reduce the noise from the digital logic. Also, differential clock distribution is used for the reference clock to all the device’s PLLs, as well as from the circuitry of those PLLs at each lane. The differential clock distribution improves the clock’s noise immunity.

Ensuring a high-speed signal – all the way down to the package

At 6.25 Gbaud, channel engineering and design is ever more critical and coupled to the transceiver. Indeed, at this rate, the Serial RapidIO Gen2 specification defers to StatEye compliant transceivers and channels.

IDT designed the switches’ Flip Chip Ball Grid Array (FCBGA) packages to meet specification requirements – the package itself is part of the channel and it’s design is performed in coordination with the chip itself, with internal BGA trace lengths minimised, lane pairs carefully matched, and characteristic impedance achieved.

To help ensure transmitted signals do not couple into receiver lanes, the CPS-1848 has ground supply isolation pins between Tx and Rx pins. Further, power supply pins divide each lane to reduce coupling from one lane into the next.

Power-Ground loop inductance is minimised by providing core Vdd and Ground in a checkerboard fashion. This allows easy application of decoupling capacitors to the PCB’s secondary side.

To improve signalling for the high-speed Serial RapidIO lines, via anti-pads are used to clear the signal via pad from the ground plane on the same layer as the pad. Excess capacitance is removed by increasing the anti-pad clearance for the laser via pad to 100um and for the core via pad from to 150um.

To minimise noise from the digital core into the high-speed SerDes and PLLs, the device and package provide separate core and analogue supply rails. A dedicated SerDes transmitter supply runs at 1.2V, though the device is fabricated on a 1.0V core process. This ensures strong transmit swing to guarantee transmitter specifications are met with margin.

Usage considerations at this performance

Over long reach at 6.25 Gbaud, there may be no eye to scope at the receiver. At these lane rates, very expensive oscilloscopes would typically be required to review the signal integrity. Further, receiver equalisation can improve the signal seen at the receiver. What an oscilloscope sees external to the device may be much worse than what is seen by the actual die, post equalisation. With receiver equalisation, On-Die Scope becomes a very useful tool to see what the device sees.

Serial RapidIO Gen2 device offerings double port speed to 20 Gbps, and are designed to meet rigorous, carrier-grade backplane applications. Key to delivering this performance is the enhanced SerDes. Device vendors must co-engineer the analogue and digital portions of their chips, and the package itself to ensure these rates are met with margin.

With the doubling of line rate and the requisite equalisation at these rates, the user may experience a paradigm shift in using these devices and characterising transceivers and channels. New vendor-specific features, such as On Die Scope and standard BER counters, will assist in this transition, and arguably make life even easier in the lab compared to other offerings.