Figure 1Chris Allsup, Marketing Manager for Synopsys’ Synthesis and Test Group, explores how Register Transfer Level code is leading to faster implementation. The register transfer level (RTL) code for today’s complex, multimillion-instance designs is typically developed by large, geographically dispersed teams and combined with third-party IP and blocks from previous chip projects.

Developing the new RTL and integrating it with the IP and legacy RTL is a time consuming process because designers lack a fast and efficient way to explore and improve the data, fix design issues and create a better starting point for RTL synthesis.

As shown in the top portion of Figure 1, the task involves multiple iterations of synthesis and refinements to the RTL and constraints. Because synthesis occurs after the design architecture is already locked-in, the process can result in a sub-optimal starting point for implementation, leading to multiple iterations throughout the flow and longer design schedules. In some situations, designers need to go back and make significant changes to the RTL before the design data is ready for easy implementation.

DC Explorer is a new tool in the Synopsys Design Compiler product line comprised of new technology to enable early RTL exploration. As shown in the bottom portion of Figure 1, it accelerates the development of high-quality RTL and constraints, helping designers create a better starting point for RTL synthesis. This article highlights several key capabilities in the product that make early RTL exploration practical and effective.

Tolerance of incomplete data

In the early stages of design development, the RTL might have missing logic and inconsistencies such as buses with different naming conventions and interfaces that are not matching. In addition, since the constraints are typically not thoroughly flushed-out early on, there could be multiple infeasible timing paths in the design.

At this early stage the designer may not have identified some paths as false paths, while other paths are actually valid and infeasible, in which case the designer may need to revise the RTL to resolve the timing issues.

The tool efficiently processes incomplete and inconsistent data, generating comprehensive reports that identify all the inconsistencies that need to be resolved. Simultaneously, it generates an easy-to-navigate, HTML-based detailed timing report the designer can use to identify problematic and infeasible timing paths.

By providing designers the capability to identify issues with the RTL and constraints and then either correct the constraints or change the RTL as needed early in the design process, it significantly shortens the early data development and refinement phase of design so implementation can begin at an earlier stage.

Usable netlists are also generated, despite incompleteness of the RTL and constraints, which the designer can use at this early stage to begin initial physical exploration floorplanning and feasibility analysis in the IC Compiler, place-and-route solution even before the RTL and constraints are complete.

Exploration across the company’s Galaxy design platform reduces unexpected iterations late in the design cycle and enables a highly convergent implementation flow using Design Compiler and IC Compiler.

The next key capability is faster runtimes: 5-10X faster than full-blown RTL synthesis. In addition, the tool supports multicore compute servers, further enabling rapid what-if exploration of multiple design configurations early in the design cycle.

The ability to perform several consecutive what-if analyses each day provides designers a significant boost in productivity levels.

An RTL exploration solution must correlate with actual synthesis results for designers to be able to determine in advance if their designs will likely meet the required timing, area, power and floorplan goals.

This brings us to the third essential feature in DC Explorer: its tight correlation with Design Compiler results.

Tight correlation with RTL synthesis QoR is critical because it provides early visibility into what synthesis results will likely be achieved. If RTL exploration reveals the design will likely not meet its QoR goals, designers can then take corrective action much earlier in the flow than previously possible.

To ensure that DC Explorer is very easy to deploy in existing flows, customers can use the same DC Ultra scripts without the need to make any changes. Early RTL exploration is now essential to accelerating design schedules in the era of “gigascale” designs.

By delivering RTL exploration that is tolerant of incomplete design data, much faster than RTL synthesis and tightly correlated with Design Compiler, the tool lets engineers perform rapid what-if analyses early in the design cycle to create a better starting point for RTL synthesis.

Early visibility into design implementation issues leads to the development of a better RTL, constraints and floorplan, reducing unexpected iterations late in the design cycle and enabling a highly convergent design flow.