Samsung Foundry’s advanced processing technologies, for high bandwidth applications, will benefit from Cadence’s developments in next-generation memory support. Planned for application fields such as high performance computing (HPC), mobile, artificial intelligence (AI), IoT, graphics, automated driving (AD) and adaptive driver assistance systems (ADAS), Cadence’s DDR5/4 PHY IP proves as a single-vendor solution that speeds chip integration time and reduces interoperability risk.

Key to the success of this is Cadence’s low bit-error rate (BER), reducing retries on the memory bus, to guarantee greater bandwidth and lower maximum latency. The use of silicon-proven DDR and SerDes designs moderates risk further, particularly when implementing advanced memory technologies. For more information on specifications and availability, follow the link to Cadence’s website: