In a joint effort, Altera Corporation and ARM have developed an embedded software development toolkit with FPGA-adaptive debug capabilities for Altera’s SoC devices.

The ARM Development Studio 5 (DS-5) Altera Edition toolkit is said to be designed to specifically target debugging barriers between the integrated dual-core CPU subsystem and FPGA fabric in Altera SoC devices.  

The two companies have combined what they claim is the most advanced multi-core debugger for the ARM architecture with the ability to adapt to the logic contained in the FPGA.

As a result the new toolkit provides full-chip visibility and control through a standard DS-5 user interface.  This toolkit will be included in the Altera SoC Embedded Design Suite and will begin shipping in early 2013.

Features include: a software debug view that adapts to include the peripheral devices programmed by the developer into the  FPGA fabric, as a resilt this enables a seamless view of both the hard and soft  peripheral register memory map of the entire SoC.

The DS-5 Debugger simultaneously displays debug/ trace data for the Cortex-A9 processor cores and  CoreSight™-compliant custom logic cores implemented in  the FPGA fabric.

An Altera USB Blaster JTAG debug cable is included that supports both the DS-5 debugger and other Altera JTAG-based tools for the Altera SoC device.

It also allows non-intrusive capture and visualisation of signal events in the FPGA fabric that can be time-correlated with software events and processor instruction trace.

The kit supports advanced, signal-level hardware cross-triggering between the CPU and FPGA logic domains, which enables cross-domain hardware/software co-debugging.

Also included is a DS-5 Streamline performance analyser, which correlates software thread and event information with hardware counters from both the SoC and FPGA, enabling the identification and correction of system-level bottlenecks.